7

Implementation of the SHA-2 Hash Family Standard Using FPGAs

Year:
2005
Language:
english
File:
PDF, 757 KB
english, 2005
9

Architectures and VLSI implementations of the AES-Proposal Rijndael

Year:
2002
Language:
english
File:
PDF, 1.49 MB
english, 2002
32

A generator for a number format conversion IC

Year:
1990
Language:
english
File:
PDF, 683 KB
english, 1990
33

Array processor for LS FIR system identification

Year:
1991
Language:
english
File:
PDF, 478 KB
english, 1991
35

Low power high-speed multithreshold voltage CMOS bus architectures

Year:
2004
Language:
english
File:
PDF, 345 KB
english, 2004
39

Full custom low-power/high performance DDP-based Cobra-H64 cipher

Year:
2010
Language:
english
File:
PDF, 2.47 MB
english, 2010
40

Multithreshold voltage low-swing/low-voltage techniques in logic gates

Year:
2004
Language:
english
File:
PDF, 344 KB
english, 2004
42

An efficient reconfigurable multiplier architecture for Galois field GF(2m)

Year:
2003
Language:
english
File:
PDF, 216 KB
english, 2003
50

Image reconstruction on a special purpose array processor

Year:
1992
Language:
english
File:
PDF, 607 KB
english, 1992